Ultrathin semiconductor circuit having contact bumps and corresponding production method

ABSTRACT

The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 11/441,978, filed May 26, 2006, which is a continuation of international application PCT/EP2004/052258, filed Sep. 21, 2004, which claims priority to German patent application serial number DE 10355508.0, filed Nov. 27, 2003, all of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method.

2. Description of the Related Art

Semiconductor circuits or semiconductor components are electrically connected to carrier substrates or leadframes by various methods including wire, flip-chip and tape automated bonding methods which represent the most important methods. While in the case of the wire bonding method, the individual connection locations or connection pads on the semiconductor circuit or the semiconductor component are successively connected to the corresponding contact locations on the leadframe by means of fine wires (bonding wires). In the case of the flip-chip and tape automated bonding methods, the contact locations or contact pads on the semiconductor circuits or chips are simultaneously contact-connected to those on the carrier substrate in one operation. Therefore, the two last-mentioned techniques are more interesting in principle to the faster contact-connection. The flip-chip and tape automated bonding techniques are gaining in importance because of the increasing number of connection pads on the semiconductor circuit or the semiconductor component.

While in the case of the wire bonding technique, no further layers have to be applied to the contact pads, which preferably comprise aluminum, on the semiconductor circuit. Since the bonding wires, which comprise gold, can be bonded directly on the aluminum surface, it is necessary, for reliably carrying out the contact-connection according to the flip-chip and tape automated bonding methods, to form so-called contact bumps made of contact-connectable and solderable materials on the contact layer elements or contact pads of the semiconductor circuits.

For flip-chip mounting, solder bumps or contact bumps are generally made of material having a high melting point. This material generally comprises a homogeneous alloy material such as Sn/Pb (95/5), which are soldered with a solder deposit situated on the carrier substrate and likewise comprising a tin-lead alloy at low temperatures. In the case of this technique, a defined distance between semiconductor circuit or chip and carrier substrate can be set during the mounting process.

However, a large number of areas of application now demand the use of so-called ultrathin semiconductor circuits or ultrathin semiconductor components having a thickness of less than 300 micrometers. While semiconductor circuits which are contact-connected according to the wire bonding method have minor problems in this case, the above-described semiconductor circuits with contact bumps exhibit an extremely low yield on account of wafer breakages of the semiconductor wafers. These low yields result from the contact bumps (on the wafer front side) which project up to 90 micrometers and, during a grinding operation (on the wafer rear side), lead to a nonuniform pressure distribution and thus to an increased wafer breakage.

Additionally, for the concluding adhesive bonding of the semiconductor component to a carrier substrate after soldering, the conventional flip-chip methods exhibit an inadequate moisture resistance and adhesion on the molding composition used for a housing.

Therefore, there is a need for an ultrathin semiconductor circuit having contact bumps and a corresponding production method, which circuit has a sufficient resistance to breaking even in the case of thicknesses of less than 300 micrometers.

SUMMARY

According to one embodiment, the limitations of prior solutions are overcome by virtue of the use of a bump supporting layer formed on a surface of a semiconductor circuit. The forces acting on projecting contact bumps during mechanical processing, such as thinning for example, can be made uniform or absorbed, as a result of which a wafer breakage can be significantly reduced and the mechanical stability of the semiconductor circuit or of a semiconductor wafer having a multiplicity of semiconductor circuits can be significantly improved. Moreover, there is an improvement in the adhesive forces between the semiconductor circuit coated with the bump supporting layer and, for example, a molding composition for a component housing as a result of which a so-called delamination is prevented and a moisture resistance is significantly improved. A long-term failure of the packaged semiconductor circuit is thereby significantly reduced.

Preferably, the thickness of the semiconductor circuit is less than 100 micrometers and the supporting layer thickness is less than the bump height and greater than or equal to the difference between bump height and half the semiconductor circuit thickness. With such a layer thickness selection, it is possible to realize breakage-resistant semiconductor wafers and thus semiconductor circuits having a thickness of well below 100 micrometers. The bump height is approximately 90 micrometers on account of shear forces acting therein.

Furthermore, the modulus of elasticity of the supporting layer is approximately half as great as the modulus of elasticity of the contact bumps, as a result of which the breakage resistance of a semiconductor circuit or a semiconductor wafer can be improved further. Preferably, photosensitive BCB (benzocyclobutene) or so-called Su-8 is used as supporting layer. Supporting layer materials of this type have optimized adhesion properties of the bump supporting layer with respect to a plastic molding composition to be used for a housing, as a result of which a sufficient moisture resistance is obtained and, in particular, the occurrence of a delamination can be prevented.

With regard to the method, a bump supporting layer is preferably formed on the surface of the semiconductor circuit and this is patterned photolithographically in order to subsequently form the bump metallization on an electrode layer by means of the electrode layer and a further patterned auxiliary layer. By means of the auxiliary layer, which is ultimately removed again, it is possible for a height of the bump metallization to be set very simply and reliably, the bump supporting layer in turn increasing the mechanical strength in particular during a grinding operation for thinning the semiconductor circuit or an associated semiconductor wafer.

Further objects, features and advantages of this invention will become readily apparent to persons skilled in the art after a review of the following description, with reference to the drawings and claims that are appended to and form a part of this specification.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F illustrate simplified sectional views for method steps in the production of an ultrathin semiconductor circuit in accordance with a first exemplary embodiment; and

FIGS. 2A to 2C illustrate simplified sectional views for method steps in the production of an ultrathin semiconductor circuit in accordance with a second exemplary embodiment.

DETAILED DESCRIPTION

Referring to FIG. 1A, a contact layer element 2 is formed in the surface of a semiconductor circuit 1, which represents a wiring surface. The contact layer element 2 may represent a so-called Al contact pad in a topmost metallization plane of a wiring layer region. Situated in the underlying layer planes (not illustrated) of the semiconductor circuit 1 or the wiring layer region thereof, there are further metallization planes or insulating intermediate layers, down to a semiconductor substrate in which the actual semiconductor components are realized.

Silicon is preferably used as semiconductor material. A multiplicity of semiconductor circuits being formed on a semiconductor wafer. Semiconductor wafers of this type initially have a thickness of 700 to 750 micrometers, for which reason they are sufficiently mechanically stable and can thus be handled in a simple manner.

In order to improve a mechanical stability in particular during a subsequent process of thinning the semiconductor wafer or the semiconductor circuit, the invention provides firstly for forming on the surface of the semiconductor circuit 1, or of a passivation layer that is usually present, a bump supporting layer 3 having a supporting layer thickness H_(P) at least in the vicinity of the contact layer element 2. A photosensitive plastic and in particular BSB (benzocyclobutene) or so-called Su-8 (procurable from Microchem, USA, www.microchem.com) is preferably used as such a bump supporting layer. These temperature-resistant and light-sensitive plastics are applied to the semiconductor circuit 1 with a predetermined supporting layer thickness H_(P) by means of conventional resist coating methods and resist coating devices. Since a height of the contact bumps to be formed is approximately 90 micrometers in order to reduce shear forces that occur, the bump supporting layer has a thickness of 50 to 80 micrometers, preferably 60 micrometers.

Furthermore, in order to ensure a sufficient moisture resistance or a low risk of a delamination, as a result of which a failure of the semiconductor circuit is prevented, the adhesion properties of the bump supporting layer 3 are optimized with regard to a molding composition that is later to be used for forming a plastic housing. So-called “underfill adhesives” used hitherto may thus be obviated since the bump supporting layer 3 has outstanding adhesion properties both with respect to the housing molding composition and with respect to the semiconductor circuit 1 or the topmost layer thereof.

Furthermore, the bump supporting layer 3 is patterned via a photolithographic patterning, in order to form at least one supporting layer opening O1 in the bump supporting layer 3. This is near the at least one contact layer element 2. The surface of the contact layer element 2 is uncovered in this way.

After the patterning of the bump supporting layer 3, a thermal annealing operation is carried out at 280 to 320 degrees Celsius, preferably at 300 degrees Celsius. As a result, of which a thermal and mechanical stabilization of the bump supporting layer 3 is carried out. In the course of this baking or curing of the bump supporting layer, the bump supporting layer 3 acquires its outstanding mechanical supporting properties which are required for the later thinning in order to avoid wafer breakage.

Referring to FIG. 1B, a subsequent step involves forming an electrode layer 4 on the surface of the patterned and cured bump supporting layer 3 and in the opening O1 directly on the surface of the semiconductor circuit 1 and the contact layer elements 2 situated therein. The electrode layer 4 is preferably formed by means of a sputtering or physical vapor deposition (PVD) method over the whole area on the wafer surface and the surface of the patterned and cured bump supporting layer 3, an approximately 200 nm/100 nm thick TiW/Cu or TiW/Ni electrode layer 4 preferably being formed. This so-called “underbump metallization” serves as a plating electrode essentially for realizing a subsequent electroplating operation and furthermore improves the mechanical properties of the contact bumps. Afterward, in accordance with FIG. 1B, an insulating auxiliary layer 5 is formed on the surface of the electrode layer 4. The auxiliary layer 5 essentially defines the overall height of the desired contact bump or the resulting bump metallization. This preferably involves carrying out resist coating by means of a conventional photoresist such as, for example, a negative resist having a thickness of 20 to 50 micrometers, preferably 40 micrometers, whereby a resulting overall height of the layers 3 to 5 of approximately 100 micrometers is obtained.

Finally, the auxiliary layer 5 is in turn patterned in order to uncover the electrode layer 4 in the region of the at least one contact layer element or contact pad 2. Once again a photolithographic patterning using the same mask as in FIG. 1A preferably being carried out. The auxiliary layer opening O2 is accordingly substantially aligned with the bump supporting layer opening O1, for which reason a depression required for the subsequent electroplating operation is now obtained.

In accordance with FIG. 10, the bump metallization is then formed on the surface of the uncovered electrode layer 4 within the openings O1 and O2. An electroplating is preferably carried out in this case. An electric current e⁻ is applied to the electrode layer 4 and metallic material from a liquid, for example, depositing on the surface of the uncovered electrode layer 4. In this case, the sections of the electrode layer 4 which are covered by the insulating auxiliary layer 5 are not coated or plated with the bump metallization in this case.

A two-stage electroplating method is preferably carried out, first with an approximately 3 to 5 micrometer thick Cu or Ni adhesion promoter metallization 6A and then an approximately 80 micrometer thick SnAg solder metallization 6B being applied. Such a multilayer structure has further improved mechanical properties on account of the adhesion promoter metallization 6A used.

Referring to FIG. 1D, the auxiliary layer 5 and the electrode layer 4 are then removed on the surface of the patterned bump supporting layer 3, the photoresist 5 preferably being stripped and the sputtered electrode layer 4 preferably being etched.

Referring to FIG. 1E, the bump metallization 6A and 6B is then subjected to remelting, the sharp edges of the bump metallization 6A and 6B being rounded at a temperature of approximately 250 degrees Celsius and the final contact bump B being completed. The completed contact bump then has a typical bump height H_(B) of approximately 90 micrometers, in which case, with a supporting layer thickness H_(P) of approximately 70 micrometers, a projection of approximately 20 micrometers results for the contact bump. Such a small projection can then be compensated for in a simple manner using conventional grinding films 7, whereby a wafer breakage is reliably prevented.

Accordingly, a processing film or grinding film 7 is then applied on the surface of the bump supporting layer 3 and the bump metallization 6A and 6B and, using said grinding film 7. The semiconductor circuit 1 is finally thinned or ground from its rear side to a desired thickness H_(S) of the semiconductor circuit 1. The processing film or grinding film 7 is finally pulled away again.

On account of the contact bumps B being embedded in the bump supporting layer 3, it is possible for the first time to produce ultrathin semiconductor circuits having a thickness H_(S) of well below 300 micrometers, a wafer breakage or the occurrence of fine cracks in the semiconductor circuit 1 being reliably prevented. A yield is accordingly for the first time also substantially increased for ultrathin semiconductor circuits having contact bumps, the overall costs thereby being significantly reduced.

Preferably, the thickness H_(S) of the semiconductor circuit 1 is less than 100 micrometers. The supporting layer thickness H_(P) of the bump supporting layer 3 is less than the bump height H_(B) of the contact bump and greater than or equal to the difference between bump height H_(B) and half the circuit thickness H_(S). When this equation

H _(S)>=2(H _(B) −H _(P))

is satisfied, it is accordingly possible to produce semiconductor circuits having contact bumps and having a thickness of less than 100 μm which have a sufficient resistance to breaking.

Furthermore, the resistance to breaking can be optimized through a targeted selection of a modulus of elasticity E_(B) for the materials of the contact bumps B and a modulus of elasticity E_(P) for the cured material of the bump supporting layer 3. It is optimal in this case, if the modulus of elasticity E_(P) of the supporting layer 3 is approximately half as great as the modulus of elasticity E_(B) of the contact bumps B. To put it more precisely, the supporting layer 3 is approximately half as hard as the contact bump B in this case.

Referring to FIG. 1F, it is further possible for a semiconductor wafer to be sawn in order to singulate the thinned semiconductor circuits 1 into singulated semiconductor components HB. The latter subsequently being contact-connected or soldered by their contact bumps B onto a carrier substrate T in accordance with a customary flip-chip bonding method. The carrier substrate T has in a customary manner connection wires A projecting from a housing formed from molding composition PM. Accordingly, the procedure finally involves encapsulating the semiconductor component HB soldered to the carrier substrate T in a molding composition PM in order to realize a packaged semiconductor component. By so doing, a reduced risk of a delamination and an improved moisture resistance being realized on account of the optimized adhesion properties of the bump supporting layer 3 is realized. A long-term failure of components can thereby be significantly reduced.

Accordingly, on account of the bump supporting layer 3, it is possible to reduce a topography of a wafer surface or a surface of a semiconductor circuit with respect to a contact bump surface from 90 micrometers to 20 micrometers. As a result, it is furthermore possible to use cost-effective standard grinding films for processing and in particular for thinning a semiconductor circuit. On account of the smaller adhesive thickness of the grinding films used, an elasticity is increased and a local penetration through the wafers is reduced, thereby significantly reducing cracking in particular during a grinding operation. Furthermore, a lateral and shearing stability of the contact bumps B is improved by the bump supporting layer 3 arranged on the sidewalls of the bump contacts B. Furthermore, no additional exposure masks or no special process materials are used, for which reason standard processes can be modified in an extremely cost-effective manner.

FIGS. 2A to 2C show simplified sectional views illustrating essential method steps in the production of an ultrathin semiconductor circuit having contact bumps in accordance with a second exemplary embodiment, identical reference symbols representing layers or elements identical or corresponding to those in FIG. 1.

Referring to FIGS. 2A to 2C, the semiconductor circuit may furthermore have a fuse element SE with an associated fuse element depression SEV such as is used for example for repairing defective switching elements by means of redundant switching elements. Such fuse elements or fuses SE are usually situated in a deeper region of the semiconductor circuit 1, for which reason a fuse element depression right into the vicinity of the fuse element SE is necessary. Such fuse elements or fuses SE can be closed or opened for example by irradiation by means of laser beams, thus resulting in a multiplicity of repair possibilities in complex semiconductor circuits. However, since the fuse element depressions SEV extend very far into the semiconductor circuit 1, they signify a particular risk for the mechanical stability particularly during a mechanical processing or during a thinning of the semiconductor circuit.

According to the invention, in accordance with FIGS. 2A to 2C, the bump supporting layer 3 is accordingly also introduced into said fuse element depressions SEV and subsequently cured. As a result, the mechanical stability of the semiconductor circuit or the semiconductor wafer can be significantly improved.

In the same way, so-called sawing frames SR are situated between adjacent semiconductor circuits, said sawing frames being required for later singulation and likewise constituting a depression in the semiconductor circuit or in the semiconductor wafer, for which reason they signify an increased risk of breakage during a grinding operation. Such sawing frames SR can also in turn be completely filled by the bump supporting layer 3, thus resulting in a reduced wafer breakage or a reduced risk of cracking during a mechanical processing or thinning of the semiconductor wafer or the semiconductor circuits.

According to the invention, through the use of a temperature-resistant bump supporting layer that remains on the semiconductor circuit or on the semiconductor wafer between the contact bumps, a topography is set to desired values of approximately 20 micrometers, for which reason standard grinding films can compensate for such height differences without any problems and a reduced wafer breakage occurs. Furthermore, the enclosing of the contact bumps B into the supporting layer 3 improves the mechanical strength of the contact bumps, for which reason the risk of a wafer breakage is once again reduced and, moreover, the risk of cracking in the semiconductor circuit is minimized. Since the bump supporting layer 3 furthermore has improved adhesion properties also with respect to an adhesive bond or a housing molding composition, improved moisture barrier properties are furthermore obtained.

As a person skilled in the art will readily appreciate, the above description is meant as an illustration of implementation of the principles this invention. This description is not intended to limit the scope or application of this invention in that the invention is susceptible to modification, variation and change, without departing from spirit of this invention, as defined in the following claims. 

1. A method for producing an ultrathin semiconductor circuit having contact bumps, the method having the steps of: preparing a semiconductor circuit having at least one contact layer element in a surface of the semiconductor surface; forming a bump supporting layer on the surface of the semiconductor circuit; patterning and curing the bump supporting layer in order to form at least one supporting layer opening in the bump supporting layer in the region of the at least one contact layer element; forming an electrode layer on the surface of the patterned and cured bump supporting layer; forming an insulating auxiliary layer on the surface of the electrode layer; patterning the insulating auxiliary layer in order to uncover the electrode layer in the region of the at least one contact layer element; forming a bump metallization on the surface of the uncovered electrode layer; removing the insulating auxiliary layer and the electrode layer on the surface of the patterned bump supporting layer; remelting the bump metallization; applying a processing film on the surface of the bump supporting layer and the bump metallization; thinning the semiconductor circuit from its rear side; and removing the processing film.
 2. The method of claim 1, wherein the contact layer element is an aluminum contact pad.
 3. The method of claim 1, wherein the step of carrying out resist coating utilizes a photosensitive material having a thickness of 50 to 80 μm.
 4. The method of claim 3, wherein the photosensitive material includes Su-8 or BCB.
 5. The method of patent claim 1, wherein the bump supporting layer is patterned by a photolithographic patterning.
 6. The method of patent claim 1, wherein the step of patterning the bum supporting layer further comprises the step of carrying out a thermal and mechanical stabilization of the bump supporting layer at approximately 300° C.
 7. The method of patent claim 1, wherein the step of forming the electrode layer further comprises the step of carrying out a sputtering for forming an approximately 200 nm/100 nm thick in particular TiW/Cu or TiW/Ni electrode layer.
 8. The method of claim 1, wherein the step forming the insulating auxiliary layer further comprises the step of carrying out resist coating with a negative resist having a thickness of 20 to 50 μm.
 9. The method of claim 1, wherein step of patterning the insulating layer further comprises the step of carrying out a photolithographic patterning of the mask from the step.
 10. The method of claim 1, wherein the step of forming the bump metallization further comprises the step of performing an electroplating process.
 11. The method of patent claim 1, wherein the bump metallization is a multilayer sequence further comprising the steps of forming an approximately 5 μm thick Cu or Ni adhesion promoter metallization and forming of an approximately 80 μm thick SnAg solder metallization (6B).
 12. The method of claim 1, wherein the step of removing the insulating auxiliary layer further comprises the step of stripping the auxiliary layer and etching the electrode layer.
 13. The method of claim 1, wherein the step of forming the insulating auxiliary layer further comprises the step of carrying out a remelting at approximately 250° C.
 14. The method of claim 1, wherein the step of removing the insulating auxiliary layer further comprises the step of carrying out a sawing of a semiconductor wafer in order to singulate the thinned semiconductor circuits into semiconductor components.
 15. The method of claim 14, further comprising the step of soldering the semiconductor component onto a carrier substrate by its contact bumps.
 16. The method of claim 15, further comprising the step of encapsulating the semiconductor component soldered to the carrier substrate in a molding composition in order to produce a packaged semiconductor component.
 17. An method for making an ultrathin semiconductor circuit having contact bumps, the method comprising: forming a contact layer element in the surface of the semiconductor circuit; forming a bump supporting layer formed on the surface of the semiconductor circuit and having a supporting layer thickness and a supporting layer opening for uncovering the contact layer element; forming an electrode layer on the surface of the contact layer element and within the supporting layer opening of the bump supporting layer; and forming a bump metallization on the electrode layer and serving for realizing the contact bumps with a bump height projecting beyond the supporting layer thickness; the ultrathin semiconductor circuit having a thickness of less than 300 micrometers.
 18. The method of claim 17, wherein the thickness of the ultrathin semiconductor circuit is less than 100 micrometers and the supporting layer thickness is less than the bump height and greater than or equal to the difference between bump height and half the thickness of the ultrathin semiconductor circuit.
 19. The method of claim 17, wherein the bump height is approximately 90 micrometers.
 20. The method of claim 17, wherein the modulus of elasticity of the supporting layer is approximately half as great as the modulus of elasticity of the contact bumps.
 21. The method of claim 17, wherein the bump supporting layer has photosensitive BCB or SU-8.
 22. The method of claim 17, further comprising the step of optimizing the adhesion properties of the bump supporting layer with regard to a molding composition to be used. 